An increase in an operation frequency and power density of a semiconductor device requires a decrease in a unit cell dimension of the semiconductor device. An approach used to reduce gate length and the unit cell size is to orient the current flow in a vertical direction using a vertical field effect transistor (FET).
The vertical FET has advantages over a standard lateral FET for high frequency, high power applications. In particular, the vertical FET eliminates parasitic capacitance and conductance from a substrate and also provides higher breakdown voltage by passing the current flow in a bulk of the material instead of the device surface. Further, since the ohmic contacts and device channel are aligned vertically, the current density per unit of surface area is much higher than in a lateral FET. Thus, for the same surface area, vertical FETs will have higher power than lateral FETs.
A vertical FET is considered as a key device structure for smaller technology nodes, e.g., 5 nm nodes and beyond. In the vertical FET, a fin can be used as a channel. Further, the source, drain, and gate are transferred from planar to vertical. However, both the source and drain contact and the contact on gate heights significantly increase in a vertical FET. The increased height will increase contact resistance and in etching selectivity on silicon nitride.